1. Field of the Invention
The present invention relates generally to the field of analog signal digitizing. More specifically the present invention is addressed to a problem of alias suppressed signal sampling at a frequency considerably lower than the upper frequency of the said analog signal. A method and apparatus covered by the invention are adapted to digitizing the high frequency signals in applications related to versatile digital signal processing (e.g. oscilloscope).
2. Description of Prior Art
For many types of the analog-to-digital (A/D) converters, the upper frequency boundary FBW of the front-end bandwidth exceeds the allowed maximum sampling rate FS considerably. For example, the A/D converter AD9433 from “Analog Devices, Inc.”, at the bandwidth FBW=700 MHz, is characterized by the maximum sampling rate FS=125 MHz. Therefore, in the cases when such A/D converters are incorporated into electronic designs based on exploitation of the conventional equidistant (uniform or periodic) sampling, the upper frequency of the analog signals at the input of the said converter has to be limited down to the level equal to FS/2 (Nyquist limit) to protect the digitized signal against aliasing.
The aliasing phenomenon is well known. The essence of it is the fact that in the cases where the original analog signal has frequencies exceeding half of the sampling rate the frequency overlapping occurs so that different frequencies might be represented by exactly the same data set and, generally, the digitized output signal bears no real relationship to the actual input signal. Therefore, to avoid aliasing in the case of the mentioned example, the upper frequency of the input analog signals has to be limited down to 62.5 MHz, to the frequency 11 times lower than the offered bandwidth of this A/D converter. In other words, the traditional approach to sampling and processing of the equidistantly sampled signals often leads to substantial under-exploitation of the bandwidth resource of the involved A/D converter.
It is known that signal sampling at predetermined non-uniformly spaced time instants can be applied for sampling an analog signal with aliasing substantially suppressed even when the mean sampling frequency FSA is essentially lower than FBW (see [1–2]). In this case, the upper frequency FBW of input analog signal spectra is limited by the minimal digital increment D of the sampling interval variation, so that FBW<½D.
However the said known methods and means for non-uniform signal sampling at predetermined time instants are oriented to fully digital implementations based on application of a special digital device controlling the sampling process at a given clock frequency Fclk in such a way that the achievable minimum value of D, determining the upper frequency of the input signal spectrum, is directly related to the maximum of the clock frequency Fclk at which the involved logic circuits still can function properly. For example, this maximum clock frequency Fclk should be at least 1.4 GHz to achieve the possibility of exploiting the whole 700 MHz bandwidth of the mentioned A/D converter. As bandwidths of the present-day A/D converters can be even much wider than 700 MHz, suppression of aliasing within the whole frequency range of their bandwidths, if attempted on the basis of the said non-uniform sampling method, would require usage of substantially higher clock frequencies measured in GHz. That clearly is not acceptable as the corresponding electronic implementations then, even when possible, would be very complicated and expensive.
Thus, to achieve alias suppression at digitizing wideband analog signals, the problem of reducing the value of the smallest clock interval digital increment D to sufficiently small values has to be resolved in a way providing that the value of D does not directly depend on the clock frequency Fclk used. For digitizing signals with the upper frequencies in hundreds of MHz and even GHz, the values of D, evidently, have to be as small as a few tens or hundreds of picoseconds.